1. Field of the Invention
The present invention relates to a data readout circuit, and more specifically, to a technology of, when a high voltage is applied to a circuit during data read-out operation, preventing erroneous writing into a data storage element and reading out the data correctly.
2. Description of the Related Art
FIG. 6 is a circuit diagram for illustrating a related-art data readout circuit of a storage device.
A PMOS transistor 11 has a source terminal connected to a power supply terminal VDD on a high voltage side. A PMOS OTP element 13 serving as a non-volatile storage element has a source terminal connected to a drain terminal of the PMOS transistor 11, and a drain terminal connected to a source terminal of a PMOS transistor 12. To a data output terminal DOUT, input and output terminals of a latch circuit 20, a drain terminal of the PMOS transistor 12, and a drain terminal of an NMOS transistor 14 are connected. The NMOS transistor 14 has a source terminal connected to a power supply terminal VSS on a low voltage side. The related-art data readout circuit of the storage device is described on the assumption that the power supply terminal VDD has a GND voltage.
A signal Φ1 is input to gates of the PMOS transistors 11 and 12, and a signal Φ2 is input to a gate of the NMOS transistor 14.
Next, an operation of the related-art data readout circuit is described.
In an initial state, the signal Φ1 is at High (VDD) level and the signal Φ2 is at Low (VSS) level, and the PMOS transistors 11 and 12 and the NMOS transistor 14 are turned off. A potential of the data output terminal DOUT is at a level of data held by the latch circuit 20, which is previously read out.
First, the signal Φ2 is set to High level to turn on the NMOS transistor 14, so that the data output terminal DOUT becomes Low level. Then, the signal Φ2 is set to Low level to turn off the NMOS transistor 14.
Next, the signal Φ1 is set to Low level to turn on the PMOS transistors 11 and 12. Consequently, data in the PMOS OTP element 13 is read out to the data output terminal DOUT, and at the same time, the data is held by the latch circuit 20. Then, the signal Φ1 is set to High level to turn off the PMOS transistors 11 and 12, but the state of the data output terminal DOUT is maintained by the latch circuit 20.
In a period of reading out data in the PMOS OTP element 13, which is 1, a voltage Vds applied between the drain and the source of the PMOS OTP element 13 is expressed by Expression (1).Vds=|VSS|−(|Vth12|+|Vov12|)  (1)
In Expression (1), Vth12 and Vov12 represent a threshold voltage and an overdrive voltage of the PMOS transistor 12, respectively. In general, the threshold voltage Vth12 is approximately −0.5 V and the overdrive voltage Vov12 is approximately −0.1 V. The drain-source voltage Vds of the PMOS OTP element 13 is −1 V when the data readout circuit is operated with a voltage of the power supply terminal VSS being −1.6 V.
However, Expression (1) depends on |VSS|. Thus, there is a problem in that, when a high voltage is applied between the power supply and the data readout circuit in a period of reading out data due to static electricity and the like, for example, the drain-source voltage Vds of the PMOS OTP element 13 is increased, and the data is erroneously written when the voltage exceeds a write voltage.
Moreover, in the related-art data readout circuit, a current of an NMOS transistor 32 (latch current), which forms the latch circuit 20 is increased with the square of a power supply voltage. On the other hand, however, a current flowing through the PMOS transistor 11, the PMOS OTP element 13, and the PMOS transistor 12 connected in series (OTP on current) is not increased so much even when the power supply voltage is increased, because a gate voltage of the PMOS OTP element 13 is a floating voltage. Thus, there is a problem in that the latch current may become larger than the OTP on current when the power supply voltage is high, with the result that data “1” cannot be read out.